Embodiments of the present disclosure disclose an array substrate and a manufacturing method thereof.
In the display technology field, panel display devices, such as thin film transistor liquid crystal displays (TFT-LCDs) and organic light emitting displays (OLEDs), have advantages of lightness, slimness, low power consumption, high-luminance as well as better display quality etc., and play a very important role in the panel display field.
Aperture ratio is an important index for determining the high-luminance of the panel display device. A higher aperture ratio creates a higher rate of light transmission. The current methods for improving aperture ratio of pixels comprises more advanced precision processing technology, decreasing areas occupied by wiring portions and the thin film transistor (TFT) of each pixel, thus improving the light transmittance of pixels.
However, due to limitation of the existing precision processing technology, such as the limitation for exposure accuracy, further minimization of a TFT is restricted. As shown in FIG. 1, a typical bottom-gate thin film transistor is illustrated, in which the gate electrode 101 is provided on a glass substrate 100, a semiconductor layer 102 is provided between the gate electrode 101 and the source and drain electrodes (the source electrode 103 and the drain electrode 104), and the source electrode 103 and the drain electrode 104 are provided at a same layer and spaced apart from an ohmic contact layer 105, and furthermore, a gate insulating layer 106 is provided between the gate electrode 101 and the semiconductor layer 102. As shown in FIG. 2, the area occupied by the TFT consists of the area occupied by the source electrode 103, the drain electrode 104 as well as the semiconductor layer 102 between the source electrode and the drain electrode.
The TFT of the above configuration is relatively large in area, and aperture ratio of the corresponding panel display device is lower. When the dimensions of the source electrode and the drain electrode are given, only the distance of the channel between the source electrode and the drain electrode can be decreased; however, a narrower channel can not be achieved due to the limited exposure accuracy of the existing exposure machines.
In addition, the alignment accuracy between the gate electrode of a TFT and the source electrode and the drain electrode of the TFT determines the degree of uniformity in display quality. One main reason for non-uniform display quality is that the capacitance C1 between the gate electrode and the source electrode does not equal to the capacitance C2 between the gate electrode and the drain electrode. By providing the gate electrode at a position in a layer different from the source electrode and the drain electrode and further the right middle between the source electrode and the drain electrode, its possible to make the capacitance C1 between the gate electrode and the source electrode approximately equal or equal to the capacitance C2 between the gate electrode and the drain electrode. However, in the existing TFT manufacturing technology, the source electrode 103 and the drain electrode 104 are made in a same layer, making it very difficult for the gate electrode 101 of each TFT to align with the source electrode 103 and the drain electrode 104, that is, difficult for the source electrode and the drain electrode to be symmetrical with respect to the gate electrode. This creates certain alignment error between the gate electrode 101 and the source and drain electrodes, and such error occurs in the structure of each TFT. With reference to the structural top view of the array substrate shown in FIG. 2, the gate electrode 101 is not aligned appropriately with the source electrode 103 and the drain electrode. If processes such as multiple exposures are needed to form all of the TFTs of a display panel, then because the TFTs formed in different exposure processes have distinct alignment error between the gate electrode 101 and the source electrode and the drain electrode, the picture chrominance corresponding to the TFTs on the entire array substrate are non-uniform, and the formed image is bad in its quality.
Moreover, in the current TFT design manner, the gate electrode comprises a certain thickness, and a certain step is formed between the gate electrode and the glass substrate, the height of the step is the thickness of the gate electrode, and the step makes the thickness of the gate insulating layer not extremely thin. If the thickness is too small, breakage of the gate insulating layer may occur. However, when the gate insulating layer is too big, a higher switching current for the TFT is required, which is adverse for improving the electrical property of the TFT.
In the current TFT configuration, the source electrode and the drain electrode are designed to be formed at a same level, and have no overlapping portions in the vertical direction, which gives rise to a relatively large TFT area, a lower aperture ratio of pixels; furthermore, in the current design manner for TFT, a greater alignment error exists between the gate electrode and the source and drain electrodes, which may cause non-uniform image chrominance for a display device, and the quality of displayed images is not good.